ßÜÜ  ÜÜÜÜܱ ÛÜÜÜÜ ÞÛÛ ßÜÜÜ Ü ± ÛÛÛßß ÛÛ² ÞÛÛÝßßÛÛÛÜÜÜ ÜÛÛÛÛ ÜÜ ÛÛÛÛÛÜÜÜÜ ÛÛÜÜ ßÛÛ² ÛÛÛ ÞÛÛÛÜÜÜÜÜÜÜÛÛÛ ÛÛÛÛÜ ÛÛÛݲÛÛ s8!CroÞÛÛÝ ÛÛÛ ÛÛÛ ßßÛÛÜ ÜÜÛßÛÛÜ ÞÛÛÛßÛÜÛÛ² ²ÛÛ ÞÛÛÛÞÛÛ² ÛÛ² ÛÛÛÝßÛÛÛÛ ÛÛÛßß Ü ²ÛÛßßßÛÛ² ²ÛÛÛßßßßßßÛÛÛÝ ²ÛÛßÛÛÛ ÞÛÛ² ²ÛÛ°°ÞÛÛÛÞÛÛÛÝ°°ÛÛ± ²ÛÛÝ°ÞÛÛ² ²ÛÛ° ÛÛÛÝ°²ÛÛÝ°°ÛÛ² ²ÛÛ °ÜÜÛÜ ²ÛÛÝ°°²ÛÛݲÛÛÝ° ÛÛ² ²ÛÛ°°ÞÛÛÛ ÛÛÛÝ°°ÛÛ° ±ÛÛÝ° ÛÛ² ²ÛÛ° ÞÛÛÛ ²ÛÛÝ°°ÛÛ² ²ÛÛ °ÞÛÛÛݲÛÛÝ°°²ÛÛ ÞÛÛÝ° ÛÛ± ²ÛÛÜÜÛÛÛÝ ßÛÛÛÜÛÛÛß °ÛÛÝ ÛÛ² ²ÛÛÜÛßßß ÞÛÛÛÝ ÜÛÛ± ²ÛÛÜÜÜÛßßßßÛÛÛÜÜÛß ÞÛÛ² ÛÛ° ßÛÛÝ ÜÜÜÜÛÜÜÜÜÜÜÜÜÜÜÜÜÜÜÛÜÜÜ ²ßß ÜÜÜÛÜÜÜÜÜÜÜÜÜÜ ²ßß ÜÜÜÜÜÛÜÜÜ ß ÜÜÜÜÜÜÜ ÞÛß ßßÜ ß Ü ± ° Ü ß ß p a n t h e o n ° p r o u d l y p r e s e n t s ÚÄÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿Ä¿ ijĴ Cadence OrCad 9.2 Complete Suite ÃÄ³Ä ÄÄÀÄÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÄÙÄÄ ÚÄÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ÂÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿Ä¿ ³ÚÙ Supplier : TEAM PANTHEON À³Ù Release Date : 12/06/2000 À¿³ ³³³ Cracker : TEAM PANTHEON ÚÙ¿ Program Type : CAD ³³³ ³³³ Packager : Willi ÀÚÙ Discs : 1CD / 23 x 15MB ³³³ ³³³ Protection: dONGLE Ú³¿ Format : .bin/.cue ³³³ ÀÄÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÁÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÄÙ ÚÄÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿Ä¿ ³ÚÙ Ä p a n t h e o n Ä Àij³ Release Information ³³ÄÙ Ä p a n t h e o n Ä À¿³ ³ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÙÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÀÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´³ ³³ ³³ ³³ Release Info: ³³ ³³ ~~~~~~~~~~~~~ ³³ ³³ In its new Orcad® Release 9.2 software, Cadence® PCB Systems Division ³³ ³³ (PSD) is shipping updates to key brands, including: Orcad Capture®, CIS, ³³ ³³ Layout, and PSpice® products, as well as overall Windows 2000® readiness. ³³ ³³ Web updates and the latest enhancements will also be included on a single ³³ ³³ CD release. Here are some of the enhancements you'll enjoy: ³³ ³³ ³³ ³³ New FPGA Design Libraries and Design Flow Support ³³ ³³ You're enabled for FPGA design. New libraries for all popular FPGAs and ³³ ³³ CPLDs are now included with Capture. Design flows are verified and ³³ ³³ documented to support Cadence VHDL Desktop and Synplicity Synplify® ³³ ³³ products. See the Cadence PSD web site ³³ ³³ (http://mainstream.pcb.cadence.com/fpga/fpgastudio.htm) for more ³³ ³³ information. ³³ ³³ ³³ ³³ Vendor Place and route system ³³ ³³ Actel Designer Series ³³ ³³ Altera MAX+Plus II or Quartus ³³ ³³ Atmel Atmel Integrated Development System (IDS) ³³ ³³ Lattice Semiconductor IspDesignEXPERT ³³ ³³ Lucent Technologies ORCA Foundry ³³ ³³ Xilinx Alliance, Foundation, or WebFitter ³³ ³³ ³³ ³³ Capture libraries and application notes for Quicklogic® ³³ ³³ (www.quicklogic.com) and Triscend® (www.triscend.com) are also available ³³ ³³ for download at factory web sites. ³³ ³³ ³³ ³³ Activeparts Plug-in for SpinCircuit.com ³³ ³³ Research and download new part data from the Internet. ³³ ³³ www.SpinCircuit.com ³³ ³³ enables you to search and select parts right off the Internet and place ³³ ³³ them directly onto your schematic page, without leaving Capture. ³³ ³³ SpinCircuit.com is the home of one million commercial and military ³³ ³³ standard parts. ³³ ³³ ³³ ³³ Better Control and Editing of Schematic Properties ³³ ³³ ³³ ³³ Control of data is a breeze with Capture's new spreadsheet editor ³³ ³³ features and reporting options. Now, you don't need to scroll across ³³ ³³ columns to view or edit a property with the new Pivot option. Simply ³³ ³³ invert object and property placement to show objects across the top row ³³ ³³ and properties down the left-hand column. The ASCII Import/Export ³³ ³³ property utility for part and net properties allows you to use external ³³ ³³ spreadsheets or database programs to add, modify, or even calculate new ³³ ³³ properties for your schematics. ³³ ³³ ³³ ³³ Improvements for PSpice Users ³³ ³³ In response to your feedback, we've implemented the top usability ³³ ³³ requests for fast and efficient analog circuit capture, including: most ³³ ³³ recently used (MRU) pick on menu bar, additional short-cut keys, and a ³³ ³³ new Analog/Mixed-Signal project wizard option that enables you to use an ³³ ³³ existing project as a template. These new features smooth the ³³ ³³ schematic/simulator cycle. ³³ ³³ ³³ ³³ LAYOUT: ³³ ³³ Manual Routing and Track Editing ³³ ³³ ³³ ³³ Single entity ³³ ³³ Tracks now move correctly with multiple components even if off grid. ³³ ³³ Manual route hinting provides control for preferred 135 (45) or 90 degree ³³ ³³ angles. Vias now move using the same hinting algorithms Numerous segment ³³ ³³ mode copper share improvements allow shared segments and vias to move as ³³ ³³ segments. Optimized manual routing to minimize creation of acute and ³³ ³³ 90-degree angles. Segment mode treats off-grid tracks the same as on-grid ³³ ³³ tracks. During manual routing, Layout displays a ratnest line to a ³³ ³³ partially routed track if it is closer than any other target pad. Layout ³³ ³³ now retains the connectivity data for copper pours and planes while ³³ ³³ manually routing. Any angle mode with real time feedback when angles are ³³ ³³ orthogonal or 45-degrees. Copy Route now copies based on net intelligence ³³ ³³ rather than by net topology. Allows user to copy tracks on repeated ³³ ³³ circuitry without having to set up matching connections ahead of time, ³³ ³³ but still adheres to netlist and DRC. Includes test points and free vias ³³ ³³ as well as tracks. DRC ³³ ³³ ³³ ³³ New "Allow DRC Errors" mode allows intentional component and track ³³ ³³ editing errors to be created with DRC markers automatically appearing and ³³ ³³ disappearing in real time. DRC options dialog settings persistent between ³³ ³³ sessions. Now, you can display DRC errors on invisible layers using ³³ ³³ dotted circles Pads, Vias and Padstack Management ³³ ³³ ³³ ³³ New user option permits moving free vias with components globally. ³³ ³³ Now you can assign colors to Free Vias. ³³ ³³ Improved padstack selection now allows you to select padstacks by Name, ³³ ³³ Height/Width, Layer, Shape, or Miscellaneous properties. For instance, ³³ ³³ you can easily pick all padstacks with 36 drill and change to 37, or pick ³³ ³³ all pad layers with rectangular padstacks of 35 by 70. Added ability to ³³ ³³ rotate pads and thermal reliefs. Layout now properly detects blind vias ³³ ³³ which are drilled from opposite sides of the board at the same X-Y ³³ ³³ location. Added ability to globally change all vias on a net to a ³³ ³³ different type. Free Via options dialog settings persistent between ³³ ³³ sessions. AutoECO ³³ ³³ ³³ ³³ AutoECO now removes only the segments nearest the component pins when ³³ ³³ removing or replacing a component during ECO. UNDO ³³ ³³ ³³ ³³ Now you can UNDO Copy Route. ³³ ³³ Plus you can UNDO Mincon. ³³ ³³ Miscellaneous ³³ ³³ ³³ ³³ ³³ ³³ Improved overall stability of Layout. ³³ ³³ Spreadsheet items are automatically updated when selecting new objects in ³³ ³³ design window. Incompletely drawn rotated square pads from Post Process ³³ ³³ output, fixed. Selected components deleted when performing Remove ³³ ³³ Violation from Board, fixed. Automatic Board Cleanup ³³ ³³ ³³ ³³ ³³ ³³ You can now select which actions are performed when Automatic Board ³³ ³³ Cleanup is activated. Additionally, you can choose to allow Automatic ³³ ³³ Board Cleanup to affect locked tracks. Select from: Miter 90-degree ³³ ³³ corners ³³ ³³ Eliminate acute angles ³³ ³³ Optimize Vertices ³³ ³³ Optimize Shared Tracks ³³ ³³ Optimize Shared Vias ³³ ³³ Optimize pad exits ³³ ³³ You can also eliminate unused padstacks, footprints or nets from the ³³ ³³ design using Auto Cleanup Design. GerbTool ³³ ³³ ³³ ³³ ³³ ³³ GerbTool design file now uses Layout's color assignments and stacks ³³ ³³ layers appropriately for IPC-D-356-Netlist Comparison. Interface and ³³ ³³ Translator ³³ ³³ ³³ ³³ SPECCTRA Autorouter interface ³³ ³³ Width by layer and clearance by layer net properties are now passed from ³³ ³³ Layout to SPECCTRA. Layout copper areas are now enclosed by route ³³ ³³ keepouts when passed to SPECCTRA. Vias embedded within pads are property ³³ ³³ changed to make SPECCTRA 34 percent faster at routing. Free via handling ³³ ³³ improved. ³³ ³³ GenCAD interface ³³ ³³ Added user control over test probe size and type. ³³ ³³ Added user control over part body definition. ³³ ³³ Added user control over test pads and test pins. ³³ ³³ DXF interface ³³ ³³ Generates 2D projection plots of Layout data onto customer specified ³³ ³³ layers. Generates drill plots for blind and buried vias. ³³ ³³ Added user control over cross-hairs in drill plots. ³³ ³³ Microsim® PCBoards translator ³³ ³³ All customer-reported bugs have been fixed. ³³ ³³ IDF interface ³³ ³³ Corrected a keepout translation bug. ³³ ³³ Corrected a mirroring/rotation bug. ³³ ³³ ³³ ³³ ³³ ³³ Installation: ³³ ³³ ~~~~~~~~~~~~~ ³³ ³³ ³³ ³³ burn with your favorite cdr-software and install :) ³³ ³³ when u r asked for serial... use the following: ³³ ³³ ³³ ³³ App Serial ³³ ³³ ---------------------------------- ³³ ³³ Capture X ³³ ³³ CaptureCIS X ³³ ³³ LayoutStd X ³³ ³³ LayoutPlus X ³³ ³³ LayoutEngEd X ³³ ³³ PSpice X ³³ ³³ PSpiceAD X ³³ ³³ PSpiceADBasics X ³³ ³³ PSpiceOptimizer X ³³ ³³ ³³ ³³ For full products u need only X,X,X,X. These includes the other ones. ³³ ³³ ³³ ³³ After that you will asked for a authorization-code. ³³ ³³ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ³³ ³³ ³³ ³À¿ ÚÙ³ ÀÄÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÄÙ ÚÄÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿Ä¿ ³ÚÙ Ä p a n t h e o n Ä Àij³ Misc Information ³³ÄÙ Ä p a n t h e o n Ä À¿³ ³ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÙÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÀÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´³ ³³ ³³ ³³ Auf einmal da. Woher? Warum? Wen juckts? Es ist einfach so. Goettlich. ³³ ³À¿ ÚÙ³ ÀÄÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙÄÙ