(view in a text editor with courier PC font or with DOS TYPE command)
Note: PentOpt has some new features not shown here. It will show actual
pipeline info as well as a line-by-line register trace.


                          ASMFLOW Professional   ($199.95)

ASMFLOW Professional is an assembly language flow charting and source
code analysis tool. ASMFLOW generates flow charts, tree diagrams, data
cross-references, register analysis, stack sizing information,
approximate timing information (8088 - Pentium) and more, directly from
your assembly language source code or listing files.

ASMFLOW is primarily a source code documentation tool, but it has a
number of features designed to help you debug and analyze your code.
For example, the register analysis feature (see next page) helps
determine the inputs and outputs of each procedure. Using ASMFLOW is
like getting a fresh objective look at your code by another programmer.


                             ASMFLOW Features:

 Flow charts                           Data Cross-reference
 Tree diagrams                         CPU timing in flow charts
 Stack sizing                          Marks recursive code
 Register analysis                     Macro expansion (80x86 only)
 Approximate CPU timing                Conditional assembly
 Instruction frequency histogram       List, wildcard or MAKE input files
 Marks instructions that affect flags  Menu, batch, or command line operation
 Comments in flow charts               Up to 1500 procedures, 5000 calls


                  Commonly asked questions about ASMFLOW:

What printers does ASMFLOW support?

   ASMFLOW supports all printers by generating only ASCII characters as
   output. The best output uses the extended-ASCII line drawing characters,
   but choices are available for printers that do not support this. Special
   HP Laserjet formats are provided for condensed printing in portrait and
   landscape modes.

Does ASMFLOW generate flow charts from .EXE files?

   No, ASMFLOW is not a disassembler. You must supply ASMFLOW with a source
   file (i.e. a .ASM file). The output of a disassembler can be used as an
   input to ASMFLOW.

Is is automatic?

   All features are completely automatic, except the approximate timing
   analysis. This feature assumes that each instruction executes one time.
   You may then insert commands (embedded in comments in the code) that
   give a minimum and a maximum number of times that a given loop or block
   of code is likely to execute. All timing information is given as a
   minimum and maximum range.

What is the register analysis?

   Each instruction in a procedure is analyzed to determine every register
   modification and use. Based on the type and order of these operations
   and every PUSH and POP, a table is generated for each procedure that
   identifies all register usage and which registers are inputs and
   outputs. (See example, next page.)

Does ASMFLOW handle macros?

   Macros are supported in two ways. First, you can specify that macros are
   to be treated as high level constructs, showing up in tree diagrams like
   a procedure call. Second, you can have macros expanded, thus becoming
   visible to the register analysis and all other ASMFLOW features.


ASMFLOW is also available for the following CPU's:

     8051 family     8080/8085         Z-80, 64180
     80x96           68HC05            68HC11
     6303            6502              1750A

These versions produce flow charts and tree diagrams, as a minimum.
Some versions include the register analysis and approximate timing
information. New features and versions are always being worked on so
call for the latest information.

If you would like a version of ASMFLOW for another CPU contact us
about doing a conversion.


Example ASMFLOW output:

                         Register Analysis Example

 space_counter proc near
 ;--------------------------------------
 ;            ax  bx  cx  dx  si  di  bp
 ; input:      0   0   1   0   1   0   0
 ; output:     2   0   1   0   1   0   0
 ; modified:   2   0   1   2   1   0   0
 ; used:       3   0   1   3   1   0   0
 ; pushed:     0   0   0   1   0   0   0
 ; popped:     0   0   0   1   0   0   0
 ;
 ; input:     cx  si
 ; output:    ax  cx  si
 ; modified:  ax  cx  dx  si
 ; used:      ax  cx  dx  si
 ; pushed:    dx
 ; popped:    dx
 ;--------------------------------------
 space_counter endp



space_counter proc near  ; Sample code
;----------------------  ; (used for flow chart and register analysis)
; inputs: DS:SI ptr to string
;         CX len of string
;
; outputs: AX   count of spaces
;----------------------

         push  dx
         xor   dx, dx   ; zero init count
loop1:   lodsb          ; read char from string
         cmp   al, ' '  ; compare to ASCII space
         jne   not_sp   ; jump if not a space
         inc   dx       ; inc count of spaces
not_sp:  loop  loop1    ; loop until end of string
         mov   ax, dx   ; return result in AX
         pop      dx
         ret

space_counter endp



      Chart style flow chart with approximate 80386 machine cycles

      Ŀ
         space_counter proc near      ; 80386 cycles
      
      Ŀ
         push   dx                    ;   2 cy
      
      Ŀ
         xor    dx, dx                ;   2 cy
      
      loop1:    
      Ŀ
     lodsb                        ;   5 cy
     
     Ŀ
        cmp    al, ' '               ;   2 cy
     
               
            /     \  not_sp
             jne  Ŀ       ;   3 cy
            \     /            
               v               
     Ŀ     
        inc    dx                   ;   2 cy
          
     not_sp:                  
     Ŀ     
  Ĵ   loop   loop1           ;  13 cy
      
      Ŀ
         mov    ax, dx                ;   2 cy
      
      Ŀ
         pop    dx                    ;   4 cy
      
      Ŀ
         ret                          ;  11 cy /  12 cy
      



Instruction Frequency Histogram

Move/xfer:     300   26% 
CMP:           115   10% 
String:        3     0%  .
Arithmetic:    71    6%  
Call/ret/jmp:  388   33% 
Bit Shift:     19    1%  
Logical:       32    2%  
Flags:         24    2%  
Push/Pop:      198   17% 



   Tree Diagram w/ timing and stack size

    Ŀ
     break_current_line                       32  
      88: 632 cy /1400 cy  126 sec / 280 sec    
     286: 306 cy / 936 cy   30 sec /  93 sec    
     386: 294 cy / 961 cy   14 sec /  48 sec    
    
      Ŀ
     Ĵ editor_warning                            48 
      
      Ŀ
     Ĵ insert_blank_line                         48 
      
      Ŀ
     Ĵ join_lines                                48 
        88: 471 cy /1021 cy   94 sec / 204 sec    
       286: 236 cy / 727 cy   23 sec /  72 sec    
       386: 223 cy / 735 cy   11 sec /  36 sec    
      
         Ŀ
        Ĵ delete_edit_line                          64 
         
         Ŀ
        Ĵ editor_line_out                           64 
          
      Ŀ
     Ĵ editor_line_out                           48 
       

    numbers in upper right corner are stack depth
    timing information is shown as min/max for cycles then min/max for seconds



            Simple Tree Diagram

       break_current_line
         editor_warning
            save_screen
            display_warning
            restore_screen
         editor_warning
         insert_blank_line
         adjust_line
         join_lines
            editor_warning
            adjust_line
            delete_edit_line
            editor_line_out
         editor_line_out
         join_lines


Other sample files available, contact us for info.








                        PentOpt Professional(TM)
                                                                $199.95

   PentOpt Professional is an assembly language source code
   optimization tool for the Intel PentiumTM and 486 processors.
   PentOpt analyzes your code and produces annotated flow charts
   with all the information you need to schedule instructions for
   maximum dual pipeline operation.

                        Features in PentOpt Pro

         Annotated Flow Charts with timing and pairing info
         Loop summary reports with loop nesting depth
         AGI (address generation interlock) detection

   For many programmers, to see how to take advantage of all this
   information and of the superscalar execution capabilities of the
   Pentium will require some additional knowledge. So that's why,

               We Wrote the Book on Pentium Optimization

   The book is PentiumTM Processor Optimization Tools, by Quantasm
   President, Mike Schmit, published by AP Professional (ISBN 0-12-
   627230-1). This book describes a step-by-step method for
   optimizing code for superscalar execution. The disk included with
   the book contains all the example source code, as well as the
   timing tools required to verify performance for 16-bit or 32-bit
   code. All this and DEBUG32, a 32-bit DPMI debugger, for only
   $39.95.

   The book provides you with the knowledge and expertise to write
   fast efficient code for the Pentium and 486; and PentOpt
   eliminates most of the tedious work of remembering all the
   details of instruction pairing and pipeline stalls. But more
   important is that PentOpt helps isolate likely candidates for
   optimization in your existing code with the use of the loop
   summary reports. In just a few seconds PentOpt can scan 1000's of
   lines of code, then you can use these reports to determine where
   to spend your time optimizing for maximum dual pipeline
   operation.

           The Pentium Superscalar Architecture: Background

   The Intel Pentium has two instruction pipelines (U and V pipes).
   The CPU will execute the next two instructions from the prefetch
   queue if certain criteria are met and the results of the first
   instruction are not needed for the second instruction. PentOpt
   checks these conditions for you. In addition PentOpt checks for
   AGI's (address generation interlocks) which can cause the CPU to
   be delayed for a cycle. (AGI's on the Pentium are a double
   penalty since two execution time slots are lost.) Avoiding AGI's
   on the Pentium is more difficult than on the 486 because they can
   sometimes be caused by any of the previous three instructions vs.
   only the previous one on the 486. AGI's are delays inserted into
   the pipeline when an address used in one cycle is being
   calculated during the previous cycle.



                  PentOpt Professional Sample Output


      3         copy1 proc               ;Pentium cycles  Notes
      4 -lbl:
      5        lodsb                    ;   2 cy          NP
      6        stosb                    ;   3 cy          NP
      7        or      al, al           ;   1 cy          UV 1
      8 -    jne     lbl              ;   1 cy           V *
      9         ret                      ;   2 cy          NP
     11         copy1 endp

     13         copy2 proc                   ;Pentium cycles  Notes
     15         lea     si, string1          ;   1 cy          UV 1
     16 -lbl2:
     17        mov     ax, [si]             ;   1 cy          UV 4 AGI-1
     18        add     si, 2                ;   1 cy          UV *
     19        cmp     al, 0                ;   1 cy          UV *
     20        je      exit2       Ŀ     ;   1 cy           V *
     21        mov     [di], ax            ;   1 cy          UV 2
     22        add     di, 2               ;   1 cy          UV *
     23        cmp     ah, 0               ;   1 cy          UV *
     24 -    jne     lbl2                ;   1 cy           V *
     25     exit:                      
     26         jmp     exit3       Ŀ     ;   1 cy /   2 cy  V 2
     27     exit2:                  
     28         mov     [di], al            ;   1 cy          UV 2
     29     exit3:                  
     30         ret                          ;   2 cy          NP
     32         copy2 endp

                   Complete Program Loop Summary Report

start  end   nest       ---Total---   ---Paired--   ---Reason not paired---
 line  line  depth  NP   U   V  UV     U   V  UV    NP  mis dup reg stk mem
    3    11    0     3   0   1   1     0   1   0     3   1   0   0   0   0
    4     8    1     2   0   1   1     0   1   0     3   0   0   0   0   0
   13    32    0     1   0   3   8     0   2   4     1   4   0   1   0   0
   16    24    1     0   0   2   6     0   2   4     0   1   0   1   0   0

                               Loop Summary legend

           start line  starting line of program, procedure or loop
           end line    ending line of program, procedure or loop
           nest depth  nesting depth of loop
           NP          number of instructions that are not pairable
          Total
           U    total number of instructions pairable in the U-pipe
           V    total number of instructions pairable in the V-pipe
           UV   total number of instructions pairable in the U- or V-pipe
          Paired
           U    number of U-pipe instructions that may be paired
           V    number of V-pipe instructions that may be paired
           UV   number of U- or V-pipe instructions that may be paired
          Reason not paired
           NP   previous instruction is not pairable
           mis  pipe mismatch; prev instruction not U or this instruction
          not V
           dup  duplicate register destination (write after write)
           reg  register conflict (read after write)
           stk  stack pointer register conflict
           mem  memory operand conflict


          Flow chart instruction notes (* = pairs; else reason not
          pairable):

           * = pairable with previous instruction
           1 = previous instruction is NP (Not pairable)
           2 = U and V pipe mismatch (previous not U or this one not V)
           3 = repeated register destination (write after write)
           4 = register conflict (read after write)
           5 = stack pointer or flags register conflict (read after write)
           6 = memory operand conflict (read or write after write)
           AGI n = Address Generation Interlock on instruction -n
