Tech Brief No. 12 The Effects of High-Speed Design Techniques and Test Equipment Measurement Bob Brown, Product Manager, EconOscillators
Figure 1: Scope trace Figure 2: Using a 10 M input impedance probe Figure 3: Results of using a 10 M input impedance probe		The DS1075K Development Kit can be used to program and reprogram devices for prototypes.

The DS1075K Demonstration Kit[1075k.pdf - MISSING] was designed as a convenient way for users to program the DS1075 EconOscillator and to demonstrate all its functional modes. The DS1075K is intended primarily as a tool for programming and preliminary evaluation of EconOscillators. The use of sockets for convenient programming precludes the possibility of providing optimum decoupling of the device. Consequently, the output waveforms present on the BNC sockets of the board may exhibit some distortion (rounding) or even slight frequency errors, particularly when operating at or near the maximum frequency. For optimum performance of the devices, they should be soldered directly to the application PCB, lead lengths should be kept to a minimum, and decoupling should be fitted as close to the device pins as possible using a suitable grade capacitor. When evaluating the parametric performance, it is important to be aware of high-speed design techniques and how test equipment can affect the measurement results. Figure 1: Scope trace The scope trace in Figure 1 shows the REF and OUT terminal waveforms from the DS1075K. A DS1075-100 with the OUT0 pin disabled is shown. The connection to the oscilloscope is made with 50 ohm impedance coaxial cable, and oscilloscope input impedence is set at 50 ohms. Note the overshoot and ringing visible at the OUT terminal, and the nearly 500 mV peak-to-peak crosstalk on the REF terminal. These effects are caused primarily by PCB trace inductance and parasitic inductance between the power supply terminals and the IC Vcc and GND pins. A new board layout was developed to minimize PCB trace lengths and provide a large, continuous ground plane. A three-capacitor bypassing scheme was used to provide a low-impedence path to ground at all transient frequencies. Highest frequency transients are shunted to ground by 1000 pF and 0.01 µF ceramic chip capacitors. These are located as close as possible to the DS1075 supply pin to minimize any series inductance and resistance. A 10 µF capacitor is placed in parallel to shunt lower frequency transients to ground. (See Reference 1.) The result is shown in Figure 2 where the OUT terminal waveform is free from overshoot, and the crosstalk amplitude is reduced to less than 120 mV peak-to-peak. Figure 2: Using a 10 M input impedance probe with a 4-inch ground lead It is also important to realize how equipment can degrade the measurement results. Figure 3 shows the results of using a 10 M input impedance probe with a 4-inch ground lead on the same circuit as used in Figure 2. The impedance mismatch creates signal reflections which appear as additional transients on the scope trace, and the long ground lead adds parasitic inductance and resistance. A detailed treatment can be found in Reference 2. Figure 3: Results of using a 10 M input impedance probe References 1. Walt Kester, "Evaluation Boards," Analog Devices High-Speed Design Techniques, 1996 2. Jim Williams, "High-Speed Amplifier Techniques," Linear Technology Applicatin Note 47, August 1991