;************************************************************* ; SYNTH.ASM ; Microprocessor control for a PLL synthesizer ;************************************************************ ; ; Controller PIC16C57 ; ; Data is shifted serially to the synthesizer - Motorola MC145170 ; Controller clock 4 MHz ; ; Author Richard Hosking ; ; *SEE REMARKS in code. few errors was fixed in original program ; *by LZ4ZD Zlatan Dimitrov lz4zd@qsl.net ; ;******************************************************************* ; carry equ 0 ; Carry bit in status register ch_1 equ 1 ; Channel 1 bit 1 port B ch_2 equ 2 ; etc ch_3 equ 3 ch_4 equ 4 ch_5 equ 5 ch_6 equ 6 ch_7 equ 7 ch_8 equ 0 ch_9 equ 1 ; Channel 9 bit 1 port C ch_10 equ 2 ; Channel 10 bit 2 etc change equ 4 ; Change bit data_C configure equ 27 ; Configuration setup for synth ; Bit 7 0 Polarity unchanged ; Bit 6 0 Differential phase det ; Bit 5 1 Lock detect enable ; Bits 432 001 Ref out enable divide by 1 ; Bit 1 1 Fv enable ; Bit 0 1 Fr enable data_B equ 0C ; Current port B status data_C equ 0D ; Port C divider_hi equ 0E ; Address of current synth data divider_lo equ 0F ; N divider FSR equ 4 ; File Select Register f4 function equ 0 ; Function bit port B ; High = 10 channels only, no display ; Low = display, 25 KHz steps OE equ 2 ; Display enable bit in port C port_A equ 5 ; Address port A port_B equ 6 ; Address port B port_C equ 7 ; Address Port C reference equ 0A0 ; Reference divider 160 for 4 MHz clock reset equ 4 ; Counter control reset bit RS equ 0 ; Display register select bit in port C R_W equ 1 ; Display Read/Write select bit rx_hi equ 10 ; Address of rx freq data rx_lo equ 11 ; N counter status equ 3 ; Address Status Register f3 synth_clock equ 1 ; Synthesizer data clock bit port A synth_data equ 2 ; Synthesizer data bit port A synth_enable equ 0 ; Synthesizer enable bit port A temp equ 8 ; Register for temporary data temp_1 equ 9 temp_2 equ 0A temp_3 equ 0B tx_hi equ 12 ; Address of tx freq data tx_lo equ 13 ; N counter tx_rx equ 3 ; Transmit/receive sense bit port C,A w equ 0 ; w is f0 (accumulator) z equ 2 ; zero bit in status register ;************************************************************ start ; ;******************************************************************** ; ; Routine to initialize ports ; ;******************************************************************** movlw b'00001000' ; Mask to set up port A tris 5 ; All outputs except bit 3 movlw 0FF ; Port B and C all inputs tris 7 ; tris 6 ; ; bcf port_A,synth_clock ; Clock low initially bsf port_A,synth_enable ; Enable high initially nop nop bcf port_A,synth_enable ; and then low to allow data to synth movlw configure ; Configuration word for synth movwf temp movlw 08 ; 8 bits movwf temp_1 loop_configure rlf temp btfsc status,carry ; Write bit to port A bsf port_A,synth_data btfss status,carry bcf port_A,synth_data bsf port_A,synth_clock ; Clock data bcf port_A,synth_clock decfsz temp_1 goto loop_configure ; THIS IS MISSED IN ORIGINAL .ASM ; REMARK BY LZ4ZD Zlatan Dimitrov bsf port_A,synth_enable ; Latch data to synth ; ; movlw 07 ; first 7 bits low of 15 bits movwf temp ; Reference divide by 160 (0A0h) bcf port_A,synth_enable loop_2 ; to give 25 KHz steps from 4 MHz clock bcf port_A,synth_data ; Data low bsf port_A,synth_clock ; Clock data into synthesizer bcf port_A,synth_clock decfsz temp goto loop_2 ; bsf port_A,synth_data bsf port_A,synth_clock ; 1 bcf port_A,synth_clock bcf port_A,synth_data bsf port_A,synth_clock ; 0 bcf port_A,synth_clock bsf port_A,synth_data bsf port_A,synth_clock ; 1 bcf port_A,synth_clock bcf port_A,synth_data bsf port_A,synth_clock ; 0 bcf port_A,synth_clock bsf port_A,synth_clock ; 0 bcf port_A,synth_clock bsf port_A,synth_clock ; 0 bcf port_A,synth_clock bsf port_A,synth_clock ; 0 bcf port_A,synth_clock bsf port_A,synth_clock ; 0 bcf port_A,synth_clock ; bsf port_A,synth_enable ; Data to R reg ; ; ;**************************************************************************** ; ; Lowkey routine ; 10 preprogrammed channels selectable by switch ; No display ; ;***************************************************************************** ;lowkey clrf data_B ; Initialize data registers clrf data_C loop_lowkey movf port_B,w ; Get current switch status xorwf data_B,w ; ?any change btfss status,z call read_switch ; If so then get data and store movf data_C,w ; Check port C also iorlw b'11111000' ; Mask bits 3-7 xorwf port_C,w ; Check against port C btfss status,z ; If changed get new data call read_switch movf data_C,w ; Check for transmit/receive iorlw b'11110111' ; Mask all but bit 3 movwf temp movf port_A,w ; Get tx/rx from port A iorlw b'11110111' ; Mask all but bit 3 xorwf temp,w ; Compare with previous data btfss status,z ; If changed update synthesizer call synthesizer ; goto loop_lowkey ; Repeat ;**************************************************************************** ; ; Place preprogrammed data into rx and tx registers ; ;************************************************************************** ; read_switch movf port_B,w ; Save switch settings movwf data_B movf port_C,w movwf data_C ; btfss data_B,ch_1 ; Channel 1 switch low? call channel_1 btfss data_B,ch_2 ; Repeat for channel 2 etc call channel_2 btfss data_B,ch_3 call channel_3 btfss data_B,ch_4 call channel_4 btfss data_B,ch_5 call channel_5 btfss data_B,ch_6 call channel_6 btfss data_B,ch_7 call channel_7 btfss data_C,ch_8 call channel_8 btfss data_C,ch_9 call channel_9 btfss data_C,ch_10 call channel_10 ; call synthesizer ; Update synthesizer retlw 0 ; channel_1 movlw 08 ; Channel 1 53.500 MHz Simplex movwf tx_hi ; A counter data movlw 52 ; M counter movwf tx_lo movlw 0A ; Rx freq 64.200 MHz (10.7 MHz offset) movwf rx_hi movlw 08 movwf rx_lo retlw 0 ;**************************************************************** ; freq for channel_1 is WRONG. PLEASE CHECK IT !!! * ; REMARK BY LZ4ZD Zlatan Dimitrov * ;**************************************************************** channel_2 movlw 08 ; 52.525 MHz Simplex movwf tx_hi ; Channel A movlw 35 movwf tx_lo movlw 09 movwf rx_hi movlw 0D5 movwf rx_lo retlw 0 ; channel_3 movlw 08 ; 52.800 MHz Simplex movwf tx_hi ; Repeater Input movlw 40 movwf tx_lo movlw 09 movwf rx_hi movlw 0EC movwf rx_lo retlw 0 ; channel_4 movlw 08 ; 52.550 MHz Simplex movwf tx_hi ; movlw 36 movwf tx_lo movlw 09 movwf rx_hi movlw 0D6 movwf rx_lo retlw 0 ; channel_5 movlw 08 ; 52.575 MHz Simplex movwf tx_hi ; movlw 37 movwf tx_lo movlw 09 movwf rx_hi movlw 0D7 movwf rx_lo retlw 0 ; channel_6 movlw 08 ; VK5 Repeater 52.750 MHz Input movwf tx_hi movlw 3E movwf tx_lo movlw 0A ; 53.750 MHz Output movwf rx_hi movlw 12 movwf rx_lo retlw 0 ; channel_7 movlw 08 ; VK6 Repeater 52.800 MHz Input movwf tx_hi movlw 40 movwf tx_lo movlw 0A ; 53.800 MHz Output movwf rx_hi movlw 14 movwf rx_lo retlw 0 ; channel_8 movlw 08 ; VK2 Repeater 52.850 MHz Input movwf tx_hi movlw 42 movwf tx_lo movlw 0A ; 53.850 MHz Output movwf rx_hi movlw 14 movwf rx_lo retlw 0 ; channel_9 movlw 08 ; VK3 Repeater 52.900 MHz Input movwf tx_hi movlw 44 movwf tx_lo movlw 0A ; 53.900 MHz Output movwf rx_hi movlw 18 movwf rx_lo retlw 0 ; channel_10 movlw 08 ; VK4 Repeater 52.950 MHz Input movwf tx_hi movlw 46 movwf tx_lo movlw 0A ; 53.950 MHz Output movwf rx_hi movlw 1A movwf rx_lo retlw 0 ; ;*************************************************************************** ; ; Synthesizer routine ; Writes 17 bits of data to the A and M dividers ; to update the synthesizer ; A data 7 bits, MSB first followed by M data 10 bits MSB first ; ;*************************************************************************** synthesizer btfsc port_A,tx_rx ; Save transmit/receive status bsf data_C,tx_rx btfss port_A,tx_rx bcf data_C,tx_rx ; btfsc data_C,tx_rx ; Transfer data to synthesizer registers movf tx_hi,w ; tx_rx bit high = transmit btfss data_C,tx_rx ; Low = receive movf rx_hi,w movwf divider_hi ; btfsc data_C,tx_rx movf tx_lo,w btfss data_C,tx_rx movf rx_lo,w movwf divider_lo ; movlw 08 ; Count for software loop movwf temp ; 16 bits to update synth divider bcf port_A,synth_clock ; Clock must be low initially bcf port_A,synth_enable ; Enable must be low to load data ; loop_hi rlf divider_hi ; Move bit from divider data into carry btfsc status,carry ; and then to synthesizer bsf port_A,synth_data btfss status,carry bcf port_A,synth_data bsf port_A,synth_clock ; Clock data to synthesizer on pos transition bcf port_A,synth_clock ; and reset for next bit decfsz temp ; next bit goto loop_hi ; movlw 08 ; count for lo byte movwf temp loop_lo rlf divider_lo ; Same for M byte btfsc status,carry bsf port_A,synth_data btfss status,carry bcf port_A,synth_data bsf port_A,synth_clock bcf port_A,synth_clock decfsz temp goto loop_lo ; bsf port_A,synth_enable ; Enable bit low to restart synthesizer retlw 0 ; Return ; end