Presented at EMC EXPO 1996, June 16-19, 1986, Washington D.C.

FUTURE EMC TRENDS IN PC BOARD DESIGN

Bruce Gabrielson, PhD

TEMPEST Consultant
PO Box 550
Chesapeake Beach, Maryland 20732

ABSTRACT

As the industry moves toward increased density, higher speeds, and lower power requirements, certain critical EMC needs in printed circuit card design have been identified. This paper addresses the limitations of current design techniques, and expected future trends in EMI PC card protection.

Where do we go from here? Since a great deal has been written in recent years concerning the proper layout and design of printed circuit cards, it would appear at first glance that the majority of PC design problems have already been solved. Emanation and coupling characteristics of circuit board traces have been defined, popular device characteristics have been measured, and the effects of grounds planes on impedance has been noted. A more precise PC board question should read, "What are the EMI related areas that need further attention in relation to industry trends during the next few years"?

FUTURE TRENDS

The major push in product design is the desire to put greater capability into less space at lower cost. This results in a drive towards more complexity and smaller size. With today's very large-scale integrated circuit technology, engineers are now able to combine a tremendous number of functions in a single chip.

Certain trends are now obvious in the electronics industry when the two primary needs, faster rates and more capacity are considered. Higher density devices and new technology will provide tremendous capacity at data rates approaching 50 MHz (hopefully). Additionally, the-need to reduce power is an inherent requirement, forcing the design of extremely low level sensitive circuitry. The limiting factor becomes the susceptibility of logic devices to self generated or locally generated interference.

Surface-mount technology is another area where the potential future benefits are tremendous. These benefits include reduced PC board size and cost, improved electrical performance due to shorter lead lengths, and high reliability. A total savings of between 5 and 50 percent is predicted as SMT techniques become operational. The most obvious initial cost identified in PC board design thus far is the software required to update current CAD system cell libraries. At least 64 new cells are needed to define site locations for the devices to be mounted.

MULTI-LAYER ARCHITECTURE

As data rates approach speeds where excessive noise is generated by active circuitry, PC board designers will be forced to use ground planes and power planes as the standard fabrication technique. The impedance of complete planes is significantly less than the impedance of circuit traces in the higher frequency range (above 5 MHz), creating the optimum conditions for reducing common impedance coupling between circuits.

The calculation of planar transmission line characteristics between the power plane and ground plane when in close proximity is well understood [1]. On board capacitance can be found from:

where, A is the board area in cubic centimeters and h is the thickness of the dielectric laminate in centimeters.

is the dielectric constant of the laminate material

The characteristic impedance in ohms of the planar transmission line is found from:

where, h is the plane separation and d is the smaller dimension of the two dimensional, parallel plane

The use of ordinary planar designed multi-layer PC boards may not be sufficient when future circuit designs require the use of extremely sensitive high speed circuitry mounted on the same board as less sensitive, noisy circuitry. When extreme intercircuit isolation is necessary, the current approach is to employ protection using the "picket fence" technique. Figure 1 describes the board composition using this technique.

Figure 1 - PC Card Picket Fence Barrier

Using the picket fence technique can provide significant crosstalk isolation on a single board without the necessity of separate ground planes between each trace layer. Separate planes between each layer provide less effective isolation plus the expense of many more laminations for a typical board. Board costs increase approximately 20% for each additional lamination required. The picket fence technique shown can provide about 80 DB isolation at higher frequencies between areas containing circuit traces. The ultimate PC board, shown in Figure 2, would include a picket fence around the entire perimeter of the card plus between the sections to be isolated. Filtered connectors could be mounted inside the fence on the board, with PC-mountable filters straddling the fence on all interface connections between isolated sections. The board is grounded, obviously, on the picket fence.

Figure 2 - Picket Fence

Along with the picket fence approach on multi-layer boards, higher speed logic must be interconnected without abrupt impedance discontinuities. Impedance (capacitance) discontinuities occur when a circuit trace makes abrupt change in direction. Figure 3 shows a 45 degree truncated trace which will reduce the voltage standing-wave ratio (VSWR) of the discontinuity. Since significant high frequency harmonics are generated during switching of most currently used higher speed digital circuitry, the incorporation of truncated traces (or even rounded "rubber band" traces) will become standard practice for PC board design very soon.

Figure 3. Truncated Corner Trace

ISOLATING FUTURE MICROCIRCUITS

If higher density, less susceptibility, and faster speeds are to be achieved, dual in-line (DIP) packaging will slowly make way to increased use of flatpack, and ultimately chip carrier devices. Each of these current devices is shown in Figure 4.

Figure 4 - Packaging Types

Belisle and Jackson [2] have evaluated DIP and flatpack devices of various device type and pinout configurations to determine individual isolation characteristics. Of significance were measurements of package configurations with the circuit die removed. Very little difference in isolation was observed when comparing various chip technologies leading to the conclusion that the major source of coupling is due to the leads within the package.

When comparing the results of DIP and flatpack isolation, the study found that considerably better isolation was observed using the flatpack design. Additionally, the arrangement of pinouts had a significant influence on internal gate isolation.

Figure 5 shows adjacent pins for a DIP device. As can be seen, a significant length of pin metal exists in close proximity. Device manufacturers will be forced to address pinout problems if they hope to increase speeds with the current DIP package.

Figure 5. Dual In-Line Construction Showing Lead Configuration at One End

Chip carriers offer the greatest potential for achieving an ultimate solution to accommodating increased speed, maximum density devices with a high level of isolation. On a chip carrier device, all four sides of the package contain leadless nearly equal length traces to the internal die. Packages are currently ceramic, and are mounted directly to the PC board on a small exposed board trace for each package trace. This technique is known as surface mounting. Work is under way to improve the mounting characteristics of these devices.

Maerschalk [3] has looked at the future trends in increasing circuit density in packages beyond chip carriers. He suggests that further increases in circuit density can be expected with the implementation of individual chips directly on boards (COB) for non-hermetic applications, and the use of multi-chip, hermetically sealed packages when required. Regardless of the ultimate packaging technique perfected, however, it is expected optimum EMC design for the next several years will be achieved at the chip carrier level.

CAD

Enough information is currently available related to coupling parameters and device characteristics, that the solution to maximum isolation and minimum interference in PC board design can now be achieved with computer aided design. CAD systems allow the user to obtain virtually instantaneous solutions to difficult PC board layout problems based on any number of decision criteria selected. The technique often used is known as decision-tree analysis.

Any decision situation where the outcome of a choice that can go several ways are known, and where the result of each outcome that may occur can be quantified, is a candidate for decision tree analysis. Even if the probability of a specific circuit achieving the desired isolation is unknown, decision criterion can still be applied to each alternative when arrayed in matrix form, and a best-of-best or best-of-worst solution can be determined. Therefore, a program that would emphasize cost, most isolation, optimum device selection, etc., is probably possible with current CAD techniques, and may be available to some degree at present. Certainly, programs will be available from several sources in the not to distant future.

ANALYSIS

Along with computer aided design, future EMC designers will rely on increased usage of computer predicted isolation levels based on software models. Already the industry is seeing more accurate and expanded usage of presently available predictive programs, such as those described by Gabrielson [4, 5] to evaluate the susceptibility levels of circuits based on direct conducted coupling. If these programs, or newer programs, can be expanded to incorporate board layout coupling parameters, possibly using a systems level approach very precise predictions can be achieved. A usable systems approach applicable to large scale interactive problems has been suggested by Gabrielson and Chin [6].

CONCLUSIONS

Following the basic assumptions that current industry goals are faster processing, greater density, less power, and less sensitivity to noise, this paper has discussed future trends governing critical EMC PC board design activity. Certain problems overlap and may involve overlapping solutions. Reduced power devices generate less interference and, therefore, will be less exposed to self-generated noise. Other problems, such as reducing adjacent lead lengths on Packages, may require a technology breakthrough. Regardless of where the future may lead, the role of EMC in the design of PC boards and board-mounted devices will remain a critical and driving influence.

REFERENCES

[1) White, D., EMI Control in the Design of Printed Circuit Boards, EMC Technology, January, 1982.

[2] Belisle, K., and Jackson, M., EMI Design Techniques For Decoupling and Isolation of Microcircuits, IEEE EMC Symposium, 1983, CH1838-2/83/0000-0207.

[3] Maerschalk, J., Chip Carriers Today and Tomorrow, Journal of Electronic Defense. February, 1986.

[4] Gabrielson, B., EMC Intercircuit Isolation, Design in Early or Risk Finishing Late and Over Budget, EMC Technology, July, 1984.

[5] Gabrielson, B., Digital Models for Use in EMC ISPICE Analysis, EMC Society Newsletter, Fall, 1984.

[6] Gabrielson, B., and Chin, W., Decentralized Approach for Power System Stability Analysis Following Lightning Events, International Aerospace Conference on Lightning and Static Electricity, Abingdon, England, March, 1982.