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versionPentOpt ProfessionalTM is an assembly language source code optimization tool for the Intel Pentium® and 486 processors.
PentOpt analyzes your code and produces annotated flow charts with all the information you need to schedule instructions for maximum dual pipeline operation.
For many programmers, to see how to take advantage of all this information and of the superscalar execution capabilities of the Pentium will require some additional knowledge. So that's why,
The book is "PentiumTM Processor Optimization Tools", by Quantasm President, Mike Schmit, published by AP Professional (ISBN 0-12- 627230-1). This book describes a step-by-step method for optimizing code for superscalar execution.
The disk included with the book contains all the example source code, as well as the timing tools required to verify performance for 16-bit or 32-bit code. All this and DEBUG32, a 32-bit DPMI debugger, for only $39.95.
The book provides you with the knowledge and expertise to write fast efficient code for the Pentium and 486; and PentOpt eliminates most of the tedious work of remembering all the details of instruction pairing and pipeline stalls. But more important is that PentOpt helps isolate likely candidates for optimization in your existing code with the use of the loop summary reports.
In just a few seconds PentOpt can scan 1000's of lines of code, then you can use these reports to determine where to spend your time optimizing for maximum dual pipeline operation.
The Intel Pentium has two instruction pipelines (U and V pipes). The CPU will execute the next two instructions from the prefetch queue if certain criteria are met and the results of the first instruction are not needed for the second instruction.
PentOpt checks these conditions for you. In addition PentOpt checks for AGI's (address generation interlocks) which can cause the CPU to be delayed for a cycle. (AGI's on the Pentium are a double penalty since two execution time slots are lost.) Avoiding AGI's on the Pentium is more difficult than on the 486 because they can sometimes be caused by any of the previous three instructions vs. only the previous one on the 486. AGI's are delays inserted into the pipeline when an address used in one cycle is being calculated during the previous cycle.
start end nest -Total-- -Paired-- ---Reason not paired---
line line depth NP U V UV U V UV NP mis dup reg stk mem
3 11 0 3 0 1 1 0 1 0 3 1 0 0 0 0
4 8 1 2 0 1 1 0 1 0 3 0 0 0 0 0
13 32 0 1 0 3 8 0 2 4 1 4 0 1 0 0
16 24 1 0 0 2 6 0 2 4 0 1 0 1 0 0
Loop Summary legend
start line starting line of program, procedure or loop
end line ending line of program, procedure or loop
nest depth nesting depth of loop
NP number of instructions that are not pairable
Total
U total number of instructions pairable in the U-pipe
V total number of instructions pairable in the V-pipe
UV total number of instructions pairable in the U- or V-pipe
Paired
U number of U-pipe instructions that may be paired
V number of V-pipe instructions that may be paired
UV number of U- or V-pipe instructions that may be paired
Reason not paired
NP previous instruction is not pairable
mis pipe mismatch; prev instruction not U or this instruction
not V
dup duplicate register destination (write after write)
reg register conflict (read after write)
stk stack pointer register conflict
mem memory operand conflict
Flow chart instruction notes (* = pairs; else reason not
pairable):
* = pairable with previous instruction
1 = previous instruction is NP (Not pairable)
2 = U and V pipe mismatch (previous not U or this one not V)
3 = repeated register destination (write after write)
4 = register conflict (read after write)
5 = stack pointer or flags register conflict (read after write)
6 = memory operand conflict (read or write after write)
AGI n = Address Generation Interlock on instruction -n
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